Home Forums Bug Reports Otimization

Viewing 1 post (of 1 total)
  • Author
  • #617

    Optimization itself works very well owing to a fix in the new release. Nelder-Mead is extremely robust and fast despite that generally it is regarded inferior to gradient type optimizers. The rest of the tools are very slow.

    – adding an Octave support environment complex parameter extraction/optimization problems can be solved with ease of archiving and plotting.
    – internal variable export from sophiticated Verilog-A device models can be implemented with a few program lines and such “strobe” devices can be placed in the binary library for a convenient use
    – nodes of “voltage” nature in the Verilog-A compiler are highly appreciated
    – at RF optimizations using s-parameters output=bias implies halt (bug_DC.bmp).
    – output=dc works but currents can be strobed only by CCVS-s. Currents can be used in plots but not in Eqn-s (bug_DCfix.bmp).
    – at DC optimizations VS drives imply halt. Norton equivalents fix the issue (bug_norton.bmp).
    – in Y=stoy() Y[1,2] and Y[2,1] are interchanged. stoh() looks fine, the rest was not tested. (ypars.png)

    Thank you very much for this “poor men’s” IC-CAP!

    Best regards,

Viewing 1 post (of 1 total)
  • You must be logged in to reply to this topic.