Home › Forums › Usage › Verilog-A files used in Qucs not working This topic has 2 replies, 2 voices, and was last updated 5 months, 3 weeks ago by QucsStudio. Viewing 3 posts - 1 through 3 (of 3 total) Author Posts 31. March 2021 at 15:40 #852 tomhajjarParticipant I’m experimenting using Verilog-A models in QucsStudio. I’m having trouble getting Verilog-A models used in Qucs to work in QucsStudio. I realize the attached file is not a “free” model but it was used in a number of examples in Qucs 31. March 2021 at 15:43 #853 tomhajjarParticipant File blocked. Trying again Attachments:You must be logged in to view attached files. 3. April 2021 at 10:41 #856 QucsStudioKeymaster Yes indeed, this is a bug. Thanks for reporting it! It will be fixed in the next release. Author Posts Viewing 3 posts - 1 through 3 (of 3 total) You must be logged in to reply to this topic.